Keynote Speakers
Rajeev Goré is an Emeritus Professor at the Australian National University. He obtained his PhD from the Computer Laboratory of the University of Cambridge in 1992. Before that he was at the University of Melbourne, completing a BSc (hons I) with a double major in Physics and Computer Science, and an MSc in design automation. He was the Associate Director of Research for the Research School of Computer Science and the Leader of the Logic and Computation Group at the ANU. His research interests include electronic voting and vote-counting, proof methods for non-classical logics, term rewriting, interactive theorem proving, automated reasoning and logic.
Title: Modular Synthesis of Certifying STV Counting Programs
Abstract: I will first explain STV counting and the parlous state of computer-counting code implemented by various Election Commissions from around Australia. I will then explain how we used Coq to specify a "vanilla" version of STV as a proof-calculus and used it to extract a computer program which not only counts votes according to this specification but also produces a certificate during the count. The specification of the certificate is derived from the counting rules. We have proved, in Coq, that if the certificate is correct with respect to its specification, then the result it encapsulates must be correct with respect to the relevant specification of STV. The certificate is designed so that an average third-year computer science student could write a computer program to check the correctness of the certificate. In particular, each political party could hire their own programmer to easily scrutiny the count produced by any computer program, including our own, that produces such certificates. The only caveat is that we require the publication of all ballots.
Jun Sun is an Associate Professor at Singapore Management University. Before joining SMU he worked at Singapore University of Technology and Design between 2010 and 2019. He was a Lee Kuan Yew Postdoc Fellow at the National University of Singapore, where he obtained his PhD in 2006. He played important roles in developing sFuzz -- a smart contract fuzzer which is based on and extends the well-known AFL fuzzer for C programs, and PAT (Process Analysis Toolkit) -- a self-contained framework for to support composing, simulating and reasoning of concurrent, real-time systems and other possible domains.
Title: Towards a Unified Framework for Neural Network Analysis
Abstract: Neural networks are a new form of programs. Like traditional programs, they suffer from bugs (e.g., adversarial samples), backdoors (e.g., embedded malicious neurons) and so on. Thus, the increasing relevance of neural networks in safe-critical systems demands systematic, scalable and rigorous methods and tools to analyze their safety and reliability. Unlike traditional programs, they are not built on logic but rather the result of statistical learning (i.e., black-box optimization). Thus, new methods and tools must be developed. In this work, I will present our ongoing effort on building a unified framework for analyzing a variety of neural networks against a variety of properties for solving a variety of analysis tasks (e.g., testing, deterministic verification, probabilistic verification, and repair). We invite the community to jointly develop the framework further.
Sanjit A. Seshia is a Professor in the Department of Electrical Engineering and Computer Sciences at the University of California, Berkeley. He received an M.S. and Ph.D. in Computer Science from Carnegie Mellon University, and a B.Tech. in Computer Science and Engineering from the Indian Institute of Technology, Bombay. His research interests are in formal methods for dependable and secure computing, with a current focus on the areas of cyber-physical systems, computer security, machine learning, and robotics. He has made pioneering contributions to the areas of satisfiability modulo theories (SMT), SMT-based verification, and inductive program synthesis. He is co-author of a widely-used textbook on embedded, cyber-physical systems and has led the development of technologies for cyber-physical systems education based on formal methods. His awards and honors include a Presidential Early Career Award for Scientists and Engineers (PECASE), an Alfred P. Sloan Research Fellowship, the Frederick Emmons Terman Award for contributions to electrical engineering and computer science education, the Donald O. Pederson Best Paper Award for the IEEE Transactions on CAD, and the IEEE Technical Committee on Cyber-Physical Systems (TCCPS) Mid-Career Award. He is a Fellow of the ACM and the IEEE.
Title: Verified Artificial Intelligence and Autonomy
Abstract: Verified artificial intelligence (AI) is the goal of designing AI-based systems that have strong, verified assurances of correctness with respect to mathematically-specified requirements. This goal is particularly important for autonomous and semi-autonomous systems. In this talk, I will consider Verified AI from a formal methods perspective and with a special focus on autonomy. I will describe the challenges for and recent progress towards attaining Verified AI, with examples from the domain of intelligent cyber-physical systems, with a particular focus on autonomous vehicles and aerospace systems.
Accepted Papers and Proceedings
Accepted papers are listed here. Please refer to the ICFEM 2020 proceedings.
Best Paper Award
The paper "Embedding Approximation in Event-B: Safe Hybrid System Design Using Proof and Refinement" by Guillaume Dupont, Yamine Aït-Ameur, Neeraj K. Singh, Fuyuki Ishikawa, Tsutomu Kobayashi, and Marc Pantel is awarded the Best Paper of ICFEM 2020.
Program
Download the program here.
Note that the workshop may have its own schedule for tea breaks and closing time. Please refer to the link below for more information.
